This invention relates to a semiconductor element, and more particularly to a method for manufacturing a CMOS (Complementary Metal-Oxide-Semiconductor) transistor.
MOS (Metal-Oxide-Semiconductor) transistors are the most important basic units in nowadays manufacturing process of a semiconductor. Because of the different kind of carriers, there are two kinds of essential structure for MOS transistors such as P-type MOS transistor and N-type transistor. Generally speaking, under the consideration of the speed of the elements, the N-type MOS transistor which utilizes the electron as the carrier is most common used. But for considering the xe2x80x9clow energy consumptionxe2x80x9d, a manufacturing process of CMOS transistor in which the P-type and N-type MOS transistors are simultaneously formed thereon is produced. Please refer to FIG. 1. FIG. 1 shows the schematical view of the known manufacturing process of a CMOS transistor gate structure. As shown in FIG. 1, after a silicon oxide insulator 11 is formed on the silicon substrate 10, a polysilicon layer 12 and a metal silicide layer 13 (generally a tungsten silicide, WSix) are sequentially formed on the silicon oxide insulator 11 to constitute an undefined pattern of the gate structure layers. However, the polysilicon layer 12 in the region of N-type MOS transistor has to dope a pentad such as phosphorous. Also, the polysilicon layer 12 in the region of P-type MOS transistor has to dope trivalent element, e.g., boron.
Nevertheless, the manufacturing process described above has a significant deficiency. The deficiency is that two kinds of dopants will diffuse from the polysilicon layer 12 outwardly to the metal silicide layer 13 and reciprocally diffuse along the grain boundary of the metal silicide layer 13 to another region of the polysilicon layer 12 (the arrow as shown in FIG. 1). This situation will cause the variation of the predicted doping concentration, moreover shift the predicted threshold voltage (VT) of the element, and influence the stability of product quality seriously. For solving this deficiency, U.S. Pat. No. 5,652,183 provides a solving method. This method is about directly depositing a silicon rich metal silicide layer (a silicon rich tungsten silicide, Si rich WSix, 2.36 less than x less than 4) for substituting the metal silicide layer 13 described above. Therefore, the route of the dopant which reciprocally diffuses along the grain boundary is blocked by doping the redundant silicon atoms into the grain boundary of the metal silicide layer 13. Consequently, the deficiency of producing the shift of the threshold voltage is improved. But the high resistance of the silicon rich tungsten silicide will cause the problem of imperfect interconnect in the sequential accomplished gate structure.
It is an object of the present invention to provide a method for manufacturing a CMOS transistor in the semiconductor manufacturing process.
It is another object of the present invention to provide a method to avoid the situation of the reciprocal diffusion along the grain boundary of the dopants in the semiconductor manufacturing process.
It is another further object of the present invention to improve the problem of high resistance of silicon rich tungsten silicide which causes the imperfect interconnect in the gate structure.
According to an aspect of the present invention, the method for manufacturing a semiconductor element includes a first silicon region, a second silicon region, and a metal silicide layer, wherein the metal silicide layer contacts with the first silicon region and the second silicon region separately, the method including steps of performing a first doping process to dope an N-type dopant into the first silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the first silicon region, and performing a second doping process to dope a P-type dopant into the second silicon region and to dope a diffusion barrier impurity into a portion of the metal silicide layer contacting with the second silicon region.
Preferably, the semiconductor element is a CMOS transistor.
Preferably, the first silicon region and the second silicon region are originally made of undoped polysilicon.
Preferably, the metal silicide layer is a tungsten silicide layer.
Preferably, the metal silicide layer separately covers on the first silicon region and the second silicon region.
Preferably, the first doping process includes steps of performing a first photolithography process for defining a first masking layer on the metal silicide layer, doping the N-type dopant and the diffusion barrier impurity respectively into a portion of the metal silicide layer which is not covered by the first masking layer, and the first silicon region formed thereunder, and removing the first masking layer.
Preferably, the second doping process includes steps of performing a second photolithography process for defining a second masking layer on the metal silicide layer, doping the P-type dopant and the diffusion barrier impurity respectively into a portion of the metal silicide layer which is not covered by the second masking layer, and the second silicon region formed thereunder, and removing the second masking layer.
Preferably, the first masking layer, the second masking layer, and the metal silicide layer further include a silicon nitride layer thereamong, and the first silicon region and the second silicon region further include a silicon oxide layer and a silicon substrate thereunder.
Preferably, the masking layers, the N-type dopant, the P-type dopant, and the diffusion barrier impurity respectively are photoresists, phosphorous dopants, boron dopants, and silicon dopants, the first silicon region and the second silicon region are originally made of undoped polysilicon, and the metal silicide layer is a tungsten silicide layer.
Preferably, the silicon oxide layer, the undoped polysilicon layer, the tungsten silicide layer, and the silicon nitride layer respectively have thicknesses within a range of 20 to 60 angstroms, 1500 to 2000 angstroms, 500 to 650 angstroms, and 1100 to 1300 angstroms.
Preferably, the phosphorous dopants are doped at a quantity within a range of 4xc3x971015 to 6xc3x971015 atoms/cm2 and at an applied energy within a range of 180 to 230 kiloeletrons voltage, the boron dopants are doped at a quantity within a range of 1xc3x971015 to 2xc3x971015 atoms/cm2 and at an applied energy within a range of 70 to 90 kiloeletrons voltage, and the silicon dopants are doped at a quantity within a range of 1xc3x971014 to 1xc3x971015 atoms/cm2 and at an applied energy within a range of 140 to 160 kiloelectrons voltage.
Preferably, the tungsten silicide layer having a ratio of silicon atoms and tungsten atoms is within a range of 2.6 to 3.0 after a portion of the tungsten silicide layer is doped by silicon dopants.
Preferably, the method further includes a step of performing a third photolithography process after the second doping process for defining a plural of gate structures on the first silicon region, the second silicon region, and the metal silicide layer.
Preferably, the second doping process is sequentially performed after the first doping process is completed.
Preferably, the first doping process is sequentially performed after the second doping process is completed.
In accordance with an aspect of the present invention, a method for manufacturing a CMOS transistor includes steps of providing a silicon substrate, forming a silicon oxide layer on the silicon substrate, forming a first silicon region and a second silicon region on the silicon oxide layer, forming a metal silicide layer on the first silicon region and the second silicon region, forming a cap layer on the metal silicide layer, performing a first doping process to dope an N-type dopants into the first silicon region and a diffusion barrier impurity into a portion of the metal silicide layer which contacts with the first silicon region, performing a second doping process to dope a P-type dopant into the second silicon region and a diffusion barrier impurity into a portion of the metal silicide layer which contacts with the second silicon region, and performing a third photolithography process for defining a plural of gate structures on the silicon oxide layer, the first silicon region, the second silicon region, the metal silicide layer, and the cap layer.
Preferably, the first silicon region and the second silicon region are originally made of undoped polysilicon, the metal silicide layer is a tungsten silicide layer, and the covering layer is a silicon nitride layer.
Preferably, the first dope embedding process includes steps of performing a first photolithography process for defining a first masking layer on the metal silicide layer, doping the N-type dopant and the diffusion barrier impurity respectively into a portion of the metal silicide layer which is not covered by the first masking layer, and the first silicon region formed thereunder, and removing the first masking layer.
Preferably, the second doping process includes steps of performing a second photolithography process for defining a second masking layer on the metal silicide layer, doping the P-type dopant and the diffusion barrier impurity respectively into a portion of the metal silicide layer which is not covered by the second masking layer, and the second silicon region formed thereunder, and removing the second masking layer.
Preferably, the masking layers, the N-type dopant, the P-type dopant, and the diffusion barrier impurity respectively are photoresists, phosphorous dopants, boron dopants, and silicon dopants, the first silicon region and the second silicon region are originally made of undoped polysilicon, and the metal silicide layer is a tungsten silicide layer.
Preferably, the silicon oxide layer, the undoped polysilicon layer, the tungsten silicide layer, and the silicon nitride layer respectively have thicknesses within a range of 20 to 60 angstroms, 1500 to 2000 angstroms, 500 to 650 angstroms, and 1100 to 1300 angstroms.
Preferably, the phosphorous dopants are doped at a quantity within a range of 4xc3x971015 to 6xc3x971015 atoms/cm2 and at an applied energy within a range of 180 to 230 kiloeletrons voltage, the boron dopants are doped at a quantity within a range of 1xc3x971015 to 2xc3x971015 atoms/cm2 and at an applied energy within a range of 70 to 90 kiloeletrons voltage, and the silicon dopants are doped at a quantity within a range of 1xc3x971014 to 1xc3x971015 atoms/cm2 and at an applied energy within a range of 140 to 160 kiloelectrons voltage.
Preferably, the tungsten silicide layer having a ratio of silicon atoms to tungsten atoms within a range of 2.6 to 3.0 after a portion of the tungsten silicide layer is doped by silicon dopants.
Preferably, the second doping process is sequentially performed after the first doping process is completed.
Preferably, the first doping process is sequentially performed after the second doping process is completed.